Explores approaches for accelerating machine learning applications, primarily inference. Through optimisations to network structure, processing architectures, and numerical representation, significant performance and efficiency improvements are possible.
Explores how the reconfigurability of hardware such as Field Programmable Gate Arrays can benefit a variety of applications that deal with uncertain environments. Building abstractions that enable exploitation of FPGA partial reconfiguration by application designers eases the challenges of design.
Explores how reconfigurable coarse grained architectures can be designed to accelerate computation while offering the flexibility to support a variety of applications. Combines hardware architecture and compile flow considerations. Considers the concept of FPGA “Overlays” as an intermediate hardware target for improved performance and flexibility.
Explores the integration of accelerators within network infrastructure to enable in-flight data processing. This results in substantial reductions in application latency, improved scaling of distributed applications, and improved application efficiency.